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    • 专利摘要:
    The invention relates to an optoelectronic device (5) comprising a first integrated circuit (6) comprising a support comprising first and second opposite faces, groups (G1, G2, G3) of sets of light-emitting diodes resting on the first face. The first integrated circuit further comprises, in the support, first elements (52) for the lateral electrical isolation of portions of the support around each assembly, and, on the second face, for each group, at least one first conductive pad (461, 462, 463) connected to the first terminal of the group and a second conductive pad (481, 482, 483) connected to the second terminal of the group. The device comprises a second integrated circuit (7) comprising third and fourth opposite faces, third conductive pads (70) on the third face electrically connected to the first and second conductive pads, the first integrated circuit being fixed on the third face of the second integrated circuit.
    公开号:FR3023066A1
    申请号:FR1456178
    申请日:2014-06-30
    公开日:2016-01-01
    发明作者:Frederic Mercier；Philippe Gilet；Xavier Hugon
    申请人:Aledia；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD The present invention relates generally to optoelectronic devices based on semiconductor materials and to their manufacturing processes. BACKGROUND OF THE INVENTION The present invention relates generally to optoelectronic devices based on semiconductor materials and to their manufacturing processes. The present invention more particularly relates to optoelectronic devices comprising light-emitting diodes formed by three-dimensional elements, in particular semiconductor microwires or nanowires. DESCRIPTION OF THE PRIOR ART Light-emitting diode optoelectronic devices are devices adapted to convert an electrical signal into electromagnetic radiation, and in particular devices for emitting electromagnetic radiation, in particular light. Examples of three-dimensional elements suitable for producing light-emitting diodes are microwires or nanowires comprising a semiconductor material based on a compound comprising predominantly at least one group III element and a group V element (for example gallium nitride). GaN), hereinafter called compound III-V, or comprising predominantly at least one group II element and a group VI element (for example zinc oxide ZnO), hereinafter called II-VI compound.
    [0002] B13126 - Stacked LEDs and driver 2 An optoelectronic device may include a plurality of light-emitting diodes and a light-emitting diode control circuit. By way of example, it may be desirable to supply the optoelectronic device with an alternating voltage, in particular the mains voltage. The control circuit of the light-emitting diodes can then be adapted to rectify the alternating voltage and selectively supply the light-emitting diodes to adapt to the instantaneous voltage across the device and, for example, to help reduce the phenomena of wobbling ( in English "flickering") of the light emitted by the light-emitting diodes. WO 2013/110029 discloses an optoelectronic device of this type. The light-emitting diodes correspond to discrete optoelectronic components which may each comprise one or more light-emitting diodes. The control circuit may correspond to an integrated circuit to which the optoelectronic components are connected. A disadvantage is that the number of light-emitting diodes connected to the integrated circuit is limited by the size of the optoelectronic components and the minimum gap to be maintained between the optoelectronic components. In addition, the method of manufacturing the optoelectronic device can be complex in that it comprises steps of connecting each optoelectronic component to the control circuit. SUMMARY Thus, an object of an embodiment is to overcome at least in part the disadvantages of light emitting diode electronic opto30 devices described above and their manufacturing processes. Another object of an embodiment is to increase the compactness of the optoelectronic device by reducing the space occupied by the light-emitting diodes.
    [0003] Another object of an embodiment is to reduce the size of the optoelectronic device comprising light emitting diodes connected in series. Another object of an embodiment is to reduce the number of steps in the method of manufacturing an optoelectronic device. Another object of an embodiment is that optoelectronic LED devices can be manufactured on an industrial scale and at low cost. Thus, an embodiment provides an optoelectronic device comprising: a first integrated circuit comprising a carrier having first and second opposing faces, groups of sets of light emitting diodes resting on the first face, each group comprising at least one set electroluminescent diodes connected in parallel and / or in series between first and second terminals, and each set of light-emitting diodes comprising a wired, conical or frustoconical semiconductor element or a plurality of wired, conical or frustoconical semiconductor elements connected in parallel, first integrated circuit further comprising, in the support, first elements of lateral electrical insulation portions of the support around each set, and, on the second side, for each group, at least a first conductive pad 25 connected to the first terminal of the group and a second stud cond connected to the second terminal of the group; and a second integrated circuit comprising third and fourth opposite faces, third conductive pads on the third face electrically connected to the first and second conductive pads, the first integrated circuit being fixed on the third face of the second integrated circuit. According to one embodiment, the support comprises a first substrate comprising opposing fifth and sixth faces, the light-emitting diodes being situated on the side of the fifth face, and comprising, for each set, the B13126 - Stacked LEDs and driver 4 minus one second conductive element isolated from the first substrate and passing through the first substrate from the fifth face to the sixth face and connected to one of the first conductive pads. According to one embodiment, the first elements are adapted to laterally electrically isolate portions of the first substrate underlying the light emitting diodes of each set. According to one embodiment, the first elements comprise insulating walls extending in the first substrate 10 from the fifth face to the sixth face. According to one embodiment, the second integrated circuit comprises thermal drains passing through the second integrated circuit from the third face to the fourth face. According to one embodiment, the device further comprises, for each set, an electrode layer covering each light-emitting diode of said assembly and a conductive layer covering the electrode layer around the light-emitting diodes of said assembly. According to one embodiment, the second element is in contact with the conductive layer. According to one embodiment, the second integrated circuit comprises a rectifier circuit for receiving an alternating voltage. According to one embodiment, the first integrated circuit comprises N groups of sets of light-emitting diodes, where N is an integer ranging from 2 to 200, and the second integrated circuit comprises N-1 switches, each switch being connected to the first terminal or the second terminal of one of said groups. According to one embodiment, the second integrated circuit comprises N current sources, each of N-1 of said current sources being connected to the first or second terminal of one of said groups.
    [0004] B13126 - Stacked LEDs and driver According to one embodiment, the device comprises fourth conductive pads on the fourth face. According to one embodiment, at least one of the groups comprises at least two sets of light-emitting diodes. BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying figures in which: FIG. partial and schematic sectional view of an embodiment of an optoelectronic light-emitting diode device; FIG. 2 is a detail view of FIG. 1 of one embodiment of the electroluminescent diodes with microwires or nanowires; FIG. 3 is a partial, schematic sectional view of another embodiment of an optoelectronic device with electroluminescent diodes with microwires or nanowires; Fig. 4 is a schematic partial sectional top view of the optoelectronic device of Fig. 1; Figures 5 to 8 are sectional, partial and schematic views of other embodiments of an optoelectronic light-emitting diode device with microwires or nanowires; and FIGS. 9 and 10 are diagrams of embodiments of the control circuit of the optoelectronic device shown in FIG. 1. DETAILED DESCRIPTION For the sake of clarity, the same elements have been designated with the same references in the various figures and, in addition, As is customary in the representation of integrated circuits, the various figures are not drawn to scale. In addition, only the elements useful for understanding the present description have been shown and are described. In particular, the logic circuits of the control circuit of the optoelectronic device described hereinafter are within the reach of those skilled in the art and are not described in detail. B13126 - Stacked LEDs and driver 6 In the remainder of the description, unless otherwise indicated, the terms "substantially", "about" and "of the order of" mean "to within 10%". In addition, "compound composed mainly of a material" or "compound based on a material" is understood to mean that a compound has a proportion greater than or equal to 95% of said material, this proportion being pre-substantially superior to 99%. The present disclosure relates to optoelectronic devices comprising light emitting diodes formed from three-dimensional elements, for example, microwires, nanowires, conical elements or frustoconical elements. In the remainder of the description, embodiments are described for light-emitting diodes formed from microfilts or nanowires. However, these embodiments may be implemented for three-dimensional elements other than microwires or nanowires, for example three-dimensional pyramid-shaped elements. The term "microfil" or "nanowire" refers to a three-dimensional structure of elongated shape in a first indication-vitreous direction of which at least two dimensions, called minor dimensions, are between 5 nm and 2.5 μm, preferably between 50 nm and 2 μm. , 5 gm, the third dimension, called major dimension, being at least equal to 1 time, preferably at least 5 times and even more preferably at least 10 times, the largest of the minor dimensions. In some embodiments, the minor dimensions may be less than or equal to about 1 μm, preferably between 100 nm and 1 μm, more preferably between 100 nm and 300 nm. In some embodiments, the height of each microfil or nanowire may be greater than or equal to 500 nm, preferably from 1 to 50 gm.
    [0005] B13126 - Stacked LEDs and driver 7 In the following description, the term "wire" is used to mean "microfil or nanowire". Preferably, the average line of the wire which passes through the barycenters of the straight sections, in planes perpendicular to the preferred direction of the wire, is substantially rectilinear and is hereinafter called "axis" of the wire. According to one embodiment, an optoelectronic device is provided comprising at least two integrated circuits, also called chips. The first integrated circuit comprises at least two sets of light-emitting diodes formed on the front face of a semiconductor substrate and electrically isolated from each other. Vertical through connections or TSV (Through Silicon Via) are made in the semiconductor substrate and isolated from the latter, each TSV connecting the front face of the substrate to the rear face. The second integrated circuit comprises electronic components, including transistors, used for controlling the sets of light emitting diodes of the first integrated circuit. The first integrated circuit is fixed to the second integrated circuit, for example by a connection of "Flip-Chip" type. The solder balls that connect the optoelectronic chip to the control chip provide the mechanical connection between the optoelectronic chip and the control chip and further ensure the electrical connection of each set of light-emitting diodes to the control chip. The first integrated circuit is called the optoelectronic circuit or optoelectronic chip in the following description and the second integrated circuit is called the control circuit or control chip in the following description. The optoelectronic chip and the control chip being stacked, the lateral size of the device is reduced. By way of example, the optoelectronic device occupies a top view of an area of between 1 mm 2 and a few square centimeters. In addition, the optoelectronic chip may have the same dimensions as the control chip. As a result, the compactness of the optoelectronic device can advantageously be increased.
    [0006] Preferably, the optoelectronic chip comprises only light-emitting diodes and connection elements of these light-emitting diodes and the control chip comprises all the electronic components necessary for controlling the light-emitting diodes of the optoelectronic chip. B13126 - Stacked LEDs and driver 8 Alternatively, the optoelectronic chip may also include other electronic components in addition to the light emitting diodes. The assembly comprising the optoelectronic chip attached to the control chip may be arranged in a protective housing. The protective housing can be attached to a support, for example a printed circuit, the electrical connections of the control chip to an external system being made through the housing. Alternatively, the control chip, on which is fixed the optoelectronic chip, can be fixed directly to the support. FIG. 1 is a partial schematic sectional view of an embodiment of an optoelectronic device 5 comprising an optoelectronic chip 6 fixed to a control chip 7, the optoelectronic chip 6 comprising light-emitting diodes made from son as described previously. By way of example, the optoelectronic chip 6 represented in FIG. 1 comprises three groups G1, G2 and G3 of sets of light-emitting diodes. Each group contains one or more sets of light emitting diodes, connected in series and / or in parallel. Each set of diodes comprises one or more diodes connected in series and / or in parallel. By diode connection in series, it is meant that the anode of one diode is connected to the cathode of the other diode. By diode connection in parallel, it is meant that the anodes of the diodes are connected together and that the cathodes of the diodes are connected together. Each set of elementary light-emitting diodes is equivalent to a light-emitting diode comprising an anode and a cathode. By serial assembly connection is meant that the anode of one set is connected to the cathode of the other. By assembly connection in parallel, it is meant that the anodes of the assemblies are connected together and that the cathodes of the assemblies are connected together. The number of groups of sets of electro-luminescent diodes depends on the intended application and can vary from 1 to 200. FIG. 1 shows an optoelectronic chip structure 6 comprising: a semiconductor substrate comprising a lower face 12 and an opposite upper face 14, the upper face 14 being preferably flat at least at the groups of sets of light-emitting diodes; groups of sets of light-emitting diodes G1, G2, G3, shown schematically, each group G1, G2, G3 comprising two electrodes, also called terminals; an insulating layer 26 extending on the face 14 of the substrate; an encapsulation layer covering the whole of the structure and in particular each group G1, G2, G3; An additional support 36, also called a handle; an insulating layer 38 covering the lower face 12; for each group G1, G2, G3, at least one TSV 401, 402, 403, two TSVs being represented in FIG. 1, each TSV 401, 402, 403 comprising a conductive portion 421, 422, 423 which is connected to the one of the electrodes of the group G1, G2, G3, which extends in the substrate 10 from the upper face 14 to the lower face 12 and which is isolated from the substrate 10 by an insulating layer 441, 442, 443, the portion conductive 421, 422, 423 extending on the insulating layer 38 by a conductive pad 461, 462, 463; conductive pads 481, 482, 483 in contact with the lower face 12 through openings 501, 502, 503 provided in the insulating layer 38; and B13126 - Stacked LEDs and driver 10 - electrically insulating means 52, for each group G1, G2, G3 of sets of light-emitting diodes, of the portion 531, 532, 533 of the substrate 10 which extends between the face 12 and the face 14 and surrounding groups of sets of light emitting diodes G1, G2, G3 associated. The optoelectronic device 5 may further comprise a phosphor layer, not shown, merged with the encapsulation layer 34, or provided between the encapsulation layer 34 and the handle 36 or provided on the handle 36.
    [0007] FIG. 2 is a detail view of FIG. 1 of an embodiment of the G1 group of light-emitting diode assemblies in which the group G1 comprises three sets D1, D2, D3 of elementary light-emitting diodes. The other groups G2 and G3 may have a similar structure to the group G1. The group G1 comprises: germination pads 161, 162, 163 promoting the growth of threads and arranged on the face 14; wires 201, 202, 203 distributed in at least two sets of wires (three sets D1, D2, D3, of five wires each, being represented by way of example in FIG. 2) of height H1, each wire 201, 202 , 203 being in contact with one of the seed pads 161, 162, 163, each wire 201, 202, 203 comprising a lower portion 221, 222, 223 of height H2, in contact with the seed pad 161, 162, 163 and an upper portion 241, 242, 243, of height H3, extending the lower portion 221, 222, 223, the insulating layer 26 extending on the lateral flanks of the lower portion 221, 222, 223 of each wire 201, 202,203; a shell 281, 282, 283 comprising a stack of 30 semiconductor layers covering each upper portion 241, 242, 243; for each set D1, D2, D3, a layer 301, 302, 303 forming an electrode covering each shell 281, 282, 283, and connecting them extending, for this, on the insulating layer 26; B13126 - Stacked LEDs and driver 11 - possibly, for each set D1, D2, D3, a conductive layer 321, 322, 323 covering the electrode layer 301, 302, 303 between the wires 201, 202, 203 but not not extending over the wires 201, 202, 203.
    [0008] In addition, in the embodiment shown in FIG. 2, the conductive pad 481 is distributed in at least one conductive pad 48'1, 48'2, 48'3 per set of wires, in contact with the lower face 12 through 50'1, 50'2, 50'3 openings provided in the insulating layer 38, each conductor pad 48'1, 48'2, 48'3 being substantially disposed vertically above the wires 201, 202, 203 of each set D1, D2, D3. In addition, the electrical insulation means 52 delimit, for each set D1, D2, D3 of light-emitting diodes, the portion 53'1, 53'2, 53'3 of the substrate 10 which extends between the faces 12 and 14 in line with the wires of the set D1, D2, D3. The wire 201, 202, 203 and the shell 281, 282, 283 associated constitute an elementary light emitting diode. In the embodiment shown in FIG. 2, each set D1, D2, D3 thus comprises several elementary light-emitting diodes connected in parallel. In the present embodiment, the support on which the elementary light-emitting diodes rest comprises the substrate 10, the insulating layer 38 and the seed pads 161, 162, 163.
    [0009] In FIG. 2, the sets D1, D2, D3 of light-emitting diodes are shown connected in series. For this purpose, the electrode 301 of the set D1 is connected to the conductive portion 421 of the TSV 401. The electrode 302 of the set D2 is connected to the portion 53'1 of the substrate associated with the set D1 and the electrode 303 of the set D3 is connected to the portion 53'2 of substrate associated with the set D2. FIGS. 1 and 2 show a control chip structure 7 comprising: a semiconductor substrate 60 comprising a lower face 62 and an opposite upper face 64; B13126 - Stacked LEDs and driver 12 - electronic components 66 formed in and / or on the substrate 60, three MOS transistors being shown by way of example in Figure 1; a stack of insulating layers 68 extending on the face 64 of the substrate 60 and on the electronic components 66 and comprising an upper face 69 vis-à-vis the optoelectronic chip 5; conductive pads 70 on the insulating layer at the top of the stack of insulating layers 68; Interconnection elements, comprising conductive tracks 72 distributed over the insulating layers 68 and conductive vias 74 passing through the insulating layers 68 and connecting the electronic components 66 and the conductive pads 70; an insulating layer 76 covering the lower face 62; - optionally, at least one TSV 78 passing through the substrate 60 which allows the connection on the rear face, the TSV 78 comprising a conductive portion 80 which is connected to one of the vias 74 and which extends in the substrate 60 of the face The upper portion 62 and which is insulated from the substrate 60 by an insulating layer 82, the conductive portion 80 extending on the insulating layer 76 by a conductive pad 84. In the present embodiment, the optoelectronic chip 6 is fixed to the control chip 7 by fusible conductor elements 86, for example solder balls or indium balls. Preferably, at least some solder balls 86 connect at least some of the conductive pads 461, 462, 463, 481, 482, 483 of the optoelectronic chip 6 to one of the conductive pads 70 of the control chip 7 and provide an electrical connection between these conductive pads. In the more detailed embodiment of the group G1 shown in FIG. 2, a single TSV 401 is associated with the group G1 which is connected to the electrode 301 of the set D1. The connection 35 between the control chip 7 and the assembly D3 is produced by the B13126 - Stacked LEDs and driver 13 48'3 conductive pad which is connected to the control chip 7 by a fusible conductor element 86. As a variant in the case where two TSVs 401 are associated with the group G1, the second TSV 401 may be connected to the substrate portion 53'3 on the side of the side 14. According to one embodiment, the series and / or parallel of the different sets of light-emitting diodes D1, D2, D3 can be made by the control chip 7. In this case, each set D1, D2, D3 of light-emitting diodes has its two connection terminals connected to the control chip 7 by fusible balls 86, one by a TSV, the other by a conductive pad 48'1, 48'2, 48'3. According to one embodiment, the control chip 7 can be fixed to an external circuit, for example a printed circuit, not shown, by solder balls 88, two of which are in contact with the conductive pads 84. In the present mode In one embodiment, the semiconductor substrate 10 corresponds to a monolithic structure. The semiconductor substrate is, for example, a substrate of silicon, germanium, silicon carbide, a III-V compound, such as GaN or GaAs, or a ZnO substrate. Preferably, the substrate 10 is a monocrystalline silicon substrate. Preferably, the semiconductor substrate 10 is doped so as to lower the electrical resistivity to a resistivity close to that of the metals, preferably less than a few mohm.cm. The substrate 10 is preferably a strongly doped substrate with a dopant concentration of between 5 * 1016 atoms / cm3 and 2 * 102 ° atoms / cm3, preferably between 1 * 1019 atoms / cm3 and 2 * 102 ° atoms / cm3, for example 5 * 1019 atoms / cm3. The substrate 10 has a thickness of between 275 and 1500 μm, preferably 725 μm. In the case of a silicon substrate 10, examples of P type dopants are boron (B) or indium (In) and examples of N type dopants are phosphorus (P), arsenic ( As), or antimony (Sb). Preferably, the B13126 - Stacked LEDs and driver substrate 14 is phosphorus-doped N-type. The face 12 of the silicon substrate 10 may be a face (100). The seed pads 161, 162, 163, also called germination islands, are made of a material that promotes the growth of the yarns 201, 202, 203. A treatment can be provided to protect the lateral flanks of the seed blocks and the surface of the parts. substrate not covered by the seed pads to prevent the growth of the son on the lateral flanks of the seed pads and on the surface of the parts of the substrate not covered by the seed pads. The treatment may comprise forming a dielectric region on the lateral flanks of the seed pads and extending on and / or in the substrate and connecting, for each pair of pads, one of the pads of the pair to the other stud of the pair, the wires not growing on the dielectric region. Said dielectric region may overflow over the seed pads 161, 162, 163. Alternatively, the seed pads 161, 162, 163 may be replaced by a seed layer covering the face 14 of the substrate 10 in the area associated with each set D1, D2 or D3. A dielectric region can then be formed above the seed layer to prevent growth of wires in the unwanted locations. By way of example, the material constituting the seed pads 161, 162, 163 may be a nitride, a carbide or a boride of a transition metal of column IV, V or VI of the periodic table of the elements or a combination of these compounds. The insulating layer 26 may be of a dielectric material, for example silicon oxide (SiO2), silicon nitride (SixNy, where x is approximately equal to 3 and y is approximately equal to 4, for example Si3N4), silicon oxynitride (SiOxNy where x may be about 1/2 and y may be about 1, eg Si2ON2), aluminum oxide (A.1203), hafnium oxide (HfO2) or in diamond. By way of example, the thickness of the insulating layer 26 is between 5 nm and 800 nm, for example equal to approximately 30 nm. The wires 201, 202, 203 are at least partly formed from at least one semiconductor material. The semiconductor material may be silicon, germanium, silicon carbide, a III-V compound, a II-VI compound or a combination thereof. The wires 201, 202, 203 may be at least partly formed from semiconductor materials predominantly having a III-V compound, for example III-N compounds. Examples of group III elements include gallium (Ga), indium (In) or aluminum (Al). Examples of III-N compounds are GaN, AlN, InN, InGaN, AlGaN or AlInGaN. Other group V elements may also be used, for example, phosphorus or arsenic. In general, the elements in compound III-V can be combined with different mole fractions. The wires 201, 202, 203 may be at least partly formed from semiconductor materials predominantly comprising a II-VI compound. Examples of Group II elements include Group IIA elements, including beryllium (Be) and magnesium (Mg) and Group IIB elements, including zinc (Zn) and cadmium (Cd). Examples of Group VI elements include elements of the VIA group, including oxygen (O) and tellurium (Te). Examples of compounds II-VI are ZnO, ZhMg0, CdZnO or CdZnMgO. In general, the elements in II-VI can be combined with different mole fractions. The wires 201, 202, 203 may comprise a dopant. By way of example, for III-V compounds, the dopant may be selected from the group comprising a Group II P dopant, for example magnesium (Mg), zinc (Zn), cadmium ( Cd) or mercury (Hg), a Group IV P-type dopant, for example carbon (C) or a Group IV N dopant, for example B13126 - Stacked LEDs and silicon driver (Si), germanium (Ge), selenium (Se), sulfur (S), terbium (Tb) or tin (Sn). The cross section of the wires 201, 202, 203 may have different shapes, such as, for example, an oval, circular or polygonal shape, in particular triangular, rectangular, square or hexagonal. Thus, it is understood that when the "diameter" in a cross-section of a wire or a layer deposited on this wire is mentioned here, it is a quantity associated with the surface of the structure referred to in this section. cross section, corresponding, for example, to the diameter of the disk having the same surface as the cross section of the wire. The average diameter of each wire 201, 202, 203 may be between 50 nm and 2.5 pin. The height H1 of each wire 201, 202, 203 may be between 250 nm and 50 pin. Each wire 201, 202, 203 may have an elongated semiconductor structure along an axis substantially perpendicular to the face 14. Each wire 201, 202, 203 may have a generally cylindrical shape. The axes of two adjacent yarns may be 0.5 to 10 μm and preferably 1.5 to 4 μm apart. By way of example, the wires 201, 202, 203 may be evenly distributed, in particular along a hexagonal network. The number of wires 201, 202, 203 may vary from one set D1, D2 and D3 to the other. By way of example, the lower portion 221, 222, 223 of each wire 201, 202, 203 consists mainly of compound III-N, for example doped gallium nitride of the same type as the substrate 10, for example type N, for example silicon. The lower portion 221, 222, 223 extends over a height H2 which can be between 100 nm and 25 pin. By way of example, the upper portion 241, 242, 243 of each wire 201, 202, 203 is at least partially made in a compound III-N, for example GaN. The upper portion 241, 242, 243 may be N-doped, possibly less strongly doped than the lower portion 221, 222, 223 or not be intentionally doped. The upper portion 241, 242, 243 extends over a height H3 which can be between 100 nm and 25 pin.
    [0010] The shell 281, 282, 283 may comprise a multilayer stack comprising in particular: an active layer covering the upper portion 241, 242, 243 of the associated wire 201, 202, 203; an intermediate layer of conductivity type opposite to the lower portion 221, 222, 223 and covering the active layer; and a bonding layer covering the intermediate layer and covered by the electrode 301, 302, 303.
    [0011] The active layer is the layer from which the majority of the radiation provided by the elementary light emitting diode is emitted. In one example, the active layer may include means for confining electric charge carriers, such as multiple quantum wells. It consists, for example, of an alternation of GaN and InGaN layers having respective thicknesses of 5 to 20 nm (for example 8 nm) and 1 to 10 nm (for example 2.5 nm). The GaN layers may be doped, for example of the N or P type. According to another example, the active layer may comprise a single layer of InGaN, for example with a thickness greater than 10 nm. The intermediate layer, for example doped P-type, may correspond to a semiconductor layer or a stack of semiconductor layers and allows the formation of a PN or PIN junction, the active layer being between the intermediate layer of type P and the N-type upper portion 241, 242, 243 of the PN or PIN junction. The bonding layer may correspond to a semiconductor layer or a stack of semiconductor layers and allows the formation of an ohmic contact between the intermediate layer and the electrode 301, 302, 303. For example, the bonding layer can be doped very strongly of the type opposite to the lower portion 221, 222, 223 of each wire 20, until degenerate the semiconductor layer or layers, for example doped P type at a concentration greater than or equal to 1020 atoms / cm3.
    [0012] B13126 - Stacked LEDs and driver 18 The semiconductor layer stack may comprise an electron blocking layer formed of a ternary alloy, for example gallium aluminum nitride (A1GaN) or indium nitride and aluminum nitride. aluminum (AlInN) in contact with the active layer and the intermediate layer, to ensure a good distribution of the electric carriers in the active layer. The electrode 301, 302, 303 is adapted to polarize the active layer of each wire 201, 202, 203 and to let the electromagnetic radiation emitted by the electroluminescent diodes pass. The material forming the electrode 301, 302, 303 may be a transparent and conductive material such as indium tin oxide (ITO), zinc oxide doped with aluminum oxide, and aluminum or gallium, or graphene. By way of example, the electrode layer 301, 302, 303 has a thickness of between 5 nm and 200 nm, preferably between 20 nm and 50 nm. The conductive layer 321, 322, 323 preferably corresponds to a metal layer, for example aluminum, silver, copper or zinc. By way of example, the conducting layer 321, 322, 323 has a thickness of between 20 nm and 1000 nm, preferably between 100 nm and 200 nm. The encapsulation layer 34 is made of at least partially transparent insulating material. The minimum thickness of the encapsulation layer 34 is between 250 nm and 50 fun so that the encapsulation layer 34 completely covers each electrode 301, 302, 303 at the top of the sets of light-emitting diodes D1, D2, D3. The encapsulation layer 34 may be made of at least partially transparent inorganic material. By way of example, the inorganic material is chosen from the group comprising silicon oxides of the SiOx type where x is a real number between 1 and 2 or SiOyNz where y and z are real numbers between 0 and 1 and aluminum oxides, for example A1203. The encapsulation layer 34 may be made of at least partially transparent organic material. For example, the encapsulation layer 34 is a silicone polymer, an epoxy polymer, an acrylic polymer, or a polycarbonate. For example, the handle 36 has a thickness of between 50 gm and 5000 gm, preferably between 200 fun and 1000 gm. The handle 36 is made of at least partly transparent material. It may be glass, especially a borosilicate glass, for example pyrex, or sapphire. According to another embodiment, the handle 36 is not present. The active layer of the shell 281, 282, 283 of the elementary light-emitting diodes of at least one of the light-emitting diode assemblies D1, D2, D3 may be manufactured in the same or different manner as the active layer of the shell of the light-emitting diodes. elements of the other sets of light-emitting diodes. For example, the active layer of the shell 281 may be adapted to emit light at a first wavelength, for example a blue light, and the active layer of the shell 282 may be adapted to emit light at a second length. wave different from the first wavelength, for example a green light. This can be achieved, for example, by adapting the thicknesses or compositions of the quantum wells composing these active layers. In the case where the active layers of the shells 281, 282 are manufactured in different ways, a first masking step can be provided to protect the assembly D2 during the production of the active layer of the shell 281 and a second masking step can be provided to protect the assembly D1 during the production of the active part of the shell 282. In addition, the assembly D3 can be adapted to emit light at a third wavelength different from the first and second wavelengths for example a red light. Thus, the composition of the blue, green, and red lights can be chosen so that an observer perceives a white light by composition of the colors, each diode, or set of diodes, emitting at a first, second and third wavelength that can be addressed independently of others to adjust the color.
    [0013] In the embodiment shown in FIG. 1, each conducting portion 421, 422, 423 may correspond to a layer or a stack of layers covering the insulating layer 441, 442, 443. The core of the TSV 401, 402, 403 may be filled wholly or only partially with a conductive material. In the embodiment described above, the TSVs 401, 402, 403 come into contact with the electrode 301, 302, 303 at the periphery of each set D1, D2, D3 of light-emitting diodes. According to another embodiment, a TSV may, in addition, be provided at each wire 201, 202, 203 of the optoelectronic chip 6. Each TSV comes into contact with the seed pad 161, 162, 163 of the associated wire. TSVs may not be connected to each other. The wires can then be polarized separately. Alternatively, an electrode provided on the side of the rear face 12 of the substrate 10, can be connected to all of the TSV associated with the same set D1, D2, D3 of light emitting diodes. According to another embodiment, a TSV can come into contact simultaneously with the seed pads 161, 162, 163 of several wires 201, 202, 203 of the same set D1, D2, D3 of light-emitting diodes. According to another embodiment, each TSV 401, 402, 403 may be formed by a filling material, for example polycrystalline silicon, tungsten or a refractory metal material which supports the thermal budget during the subsequent steps of the manufacturing process of the invention. 6. The polycrystalline silicon advantageously has a coefficient of thermal expansion close to silicon and thus makes it possible to reduce the mechanical stresses during the subsequent steps carried out at high temperatures of the process for manufacturing the optoelectronic chip 6. Another embodiment, instead of forming a TSV with a filler material isolated from the substrate 10 by insulating walls, the TSV can be made by isolation trenches delimiting a portion of the substrate which then acts as the conductive portion of the TSV. Preferably, highly doped silicon, for example having a dopant concentration greater than or equal to 1019 atoms / cm 3, is used to reduce the resistance of this connection. In the present embodiment, the electrical insulation means 52 comprise trenches extending over the entire thickness of the substrate 10 and filled with an insulating material, for example an oxide, in particular silicon oxide, or an insulating polymer. Alternatively, the electrical insulation of each substrate portion 10 associated with each diode is made by the TSV 401. In another variant, the electrical insulation walls 52 comprise doped regions of a type of opposite polarity. to the substrate 10 and extending over the entire depth of the substrate 10. According to another embodiment, the substrate 10 may not be present. A mirror layer can then be disposed on the underside of the optoelectronic chip in contact with the seed pads 161, 162, 163. According to one embodiment, the mirror layer is adapted to reflect at least in part the radiation emitted by the diodes. electroluminescent electrons. The mirror layer may be covered with at least one metal layer. The insulating layer 38 then directly covers the mirror layer (or the metal layer if it is present). The conductive pads 461, 462, 463, 481, 482, 483 are formed on the insulating layer 38 as previously described. In this embodiment, the support on which the elementary light-emitting diodes rest comprises the seed pads, the mirror layer and the conductive pads. FIG. 3 shows another embodiment of an optoelectronic device 90 comprising all the elements of the optoelectronic device 5 and in which the control chip 7 further comprises thermal drains 92, two thermal drains 92 being represented. As an example in FIG. 3. The thermal drains 92 advantageously allow B13126 - Stacked LEDs and driver 22 to improve the evacuation of the heat produced by the optoelectronic chip 6 during operation. Preferably, each heat sink 92 extends over the entire thickness of the control chip 7. Each heat sink 92 consists of a stack of materials that are good conductors of heat. Preferably, the portion of the heat sink 92 which extends into the substrate 60 is electrically isolated from the substrate 60 and may have a structure similar to a TSV as described above. In one example, the heat sink 92 may not be connected to the optoelectronic chip. This is the case of the heat sink 92 shown on the left in FIG. 3. In another example, the heat sink 92 can be connected, by a solder ball 86, to a conductive pad 93, as is the case with the heat sink 92 shown on the right in FIG. 3, disposed on a zone of the substrate of the optoelectronic chip isolated from the electrically active zones, or because it consists of a zone of the substrate completely isolated from the remainder of the substrate by trenches filled with electrical insulator or because it consists of an area of the substrate covered by an electrically insulating layer. Figure 4 is a section of Figure 2 along line IV-IV. In this figure, the electrical insulation walls 52 are shown completely surrounding the portion of the substrate 10 associated with each set of light-emitting diodes D1, D2, D3. However, alternatively, for each pair of light-emitting diode assemblies, an electrical insulation wall 52 may be provided only between the two adjacent assemblies over the entire width of the optoelectronic chip 6. By way of example in the section plane of FIG. 4, each electrical insulation wall may have a width of between 200 nm and 250 μm and preferably between 5 μm and 30 μm. In the embodiment described above, the insulating layer 26 covers the entire periphery of the lower portion 221, 222, 223 of each wire 201, 202, 203. Alternatively, a portion of the lower portion 221, 222 , 223, or even B13126 - Stacked LEDs and driver 23 the entire lower portion 221, 222, 223, may not be covered by the insulating layer 26. In this case, the shell 281, 282, 283 may cover each wire 20 on a height greater than H3, or even the height H1. In addition, in the embodiment described above, the insulating layer 26 does not cover the periphery of the upper portion 241, 242, 243 of each wire 201, 202, 203. Alternatively, the insulating layer 26 may cover a portion of the upper portion 241, 242, 243 of each wire 201, 202, 203. In another embodiment, the insulating layer 26 may, for each wire 201, 202, 203, partially cover the lower portion of the wire. the shell 281, 282, 283. In the embodiments shown in Figures 1, 2 and 3, the optoelectronic device 5 is electrically connected to an external circuit by the solder balls 88 provided on the underside of the chip. 7. However, other modes of electrical connection may be considered. FIG. 5 shows another embodiment in which the control chip 7 is electrically connected to an external circuit, for example a printed circuit, not shown, by wires 94 which are connected to the upper face 69 of the chip of FIG. control 7 on which the optoelectronic chip 6 is fixed. FIG. 6 represents another embodiment in which the optoelectronic chip 6 is electrically connected to an external circuit, for example a printed circuit, not shown, by wires 95 which are connected from the top side of the optoelectronic chip 6 to conductive pads. FIG. 7 shows another embodiment in which the optoelectronic chip 6 is electrically connected to an external circuit, for example a printed circuit, not shown, by solder balls 96 which are connected on the side of the lower face 12 of FIG. Optoelectronic chip 6. FIG. 8 represents another embodiment in which the optoelectronic chip 6 is electrically connected to an external circuit, for example a printed circuit, not shown, by soldering balls. B13126 - Stacked LEDs and driver 24 which are connected to the upper face 69 of the control chip 7. The embodiments shown in FIGS. 5 to 8 advantageously make it possible to fix the rear face of the control chip 7 to a thermally conductive support to which the drains can be connected. This improves the evacuation of the heat produced in the control chip 7. According to one embodiment, the The method of manufacturing the optoelectronic device 5 comprises the following steps: - manufacturing of the optoelectronic chip 6; - manufacture of the control chip 7; - assembly of the optoelectronic chip 6 with the control chip 7; optionally, placing the stack of the control chip 7 and the optoelectronic chip 6 in a protective case; and - fixing the stack of the control chip 7 and the optoelectronic chip 6 on a support. One embodiment of a method of manufacturing light-emitting diode assemblies D1, D2, D3 is disclosed in WO2014 / 044960 and FR13 / 59413 which will be considered as an integral part of the present disclosure. One embodiment of the TSV 421 of the light emitting diode group G1, according to the embodiment shown in FIG. 2, comprises the following steps, the TSV 422, 423 being able to be realized simultaneously in the same way: (1) Etching of at least one opening through the insulating layer 38, the substrate 10, the insulating layer 26 to expose the electrode layer 301. This opening may have a circular or rectangular cross section. Preferably, the electrode layer 301 is also etched to expose a portion of the metal layer 321. The etching of the substrate 10 may be a deep reactive ion etching (DRIE), which is English acronym for Deep Reactive Ion Etching. The etching of the portion B13126 - Stacked LEDs and driver 25 of the insulating layer 26 is also performed by plasma etching with the chemistry adapted to the insulating layer 26. At the same time, the electrode layer 301 can be etched. Alternatively, the layer 301 can be removed from the formation areas of the TSVs prior to the step of forming the metal layer 321. Trenches for making the electrical insulation walls 52 can be made simultaneously with the openings provided for the TSVs. (2) Formation of the insulating layer 441 for example of SiO2 or SiON on the layer 38 and on the inner walls of the opening etched in step (1). The insulating layer 441 is, for example, made by conformal deposition by PECVD (Plasma Enhanced Chemical Vapor Deposition) or by conformal deposition of an insulating polymer. The insulating layer 441 has a thickness between 200 nm and 5000 nm, for example about 3 pin. The insulating layer 441 may be formed at the same time as the electrical insulating walls 52. (3) Etching the insulating layer 441 to expose the conductive layer 321 at the bottom of the opening etched in step (2). This is an anisotropic etching. (4) Engraving at least one opening 501 in the insulating layer 38 to expose a portion of the face 12 of the substrate 10. To achieve this etching, the opening etched in step (1) can be temporarily blocked, by example by a resin. (5) Filling the TSV and forming the conductive pads 461, 48'1, 48'2, 48'3. The filling of the TSVs can be performed by electrolytic deposition of copper. The deposit is then planarized with a chemical mechanical polishing step (CMP). Then, a metal deposit can resume contact on the pads for the transfer on the face 12 of the substrate 10. Alternatively, the TSV 401 can be made on the side of the upper face 14 of the substrate 10, for example before formation Hulls 281, 282, 283. The TSV 401 are then made only on a part of the thickness of the substrate 10 and are exposed on the side of the lower face 12 of the substrate 10 after a B13126 - Stacked LEDs and driver 26 step d Thinning of the substrate 12. The filling of the TSV can then be carried out by chemical vapor deposition (CVD) and the isolation of the TSV can be done by thermal oxidation.
    [0014] The method of manufacturing the control chip 7 may comprise the conventional steps of a method of manufacturing an integrated circuit and is not described in more detail. The methods of assembling the optoelectronic chip 6 on the control chip 7 may include brazing operations. The metal stack forming the conductive pads 461, 462, 463, 481, 482, 483, 70 is chosen so as to be compatible with the soldering operations used in the electronics industry and in particular with the solder used, for example. example in Cu with finish OSP (acronym for Organic Solderability Preservative) or finish Ni-Au (chemically, in particular to obtain a structure of the type ENIG, acronym for Electroless Nickel Immersion Gold, or electrochemically), Sn, Sn-Ag, Ni-Pd-Au, Sn-Ag-Cu, Ti-Wn-Au or ENEPIG (acronym for Electroless Nickel / Palladium Electroless / Immersion Gold). FIG. 9 represents an equivalent electrical diagram of an embodiment of the optoelectronic device 5 in which the control chip 7 is adapted to control the groups of light-emitting diodes of the optoelectronic chip 6 from an AC supply voltage. However, it is clear that the electrical diagram shown in FIG. 9 is only one embodiment and that the functions performed by the control chip 7 are to be adapted as a function of the intended use of the optoelectronic device 5.
    [0015] In this embodiment, the control chip 7 comprises two input terminals IN 'and IN2 intended to receive a supply voltage VALIm. By way of example, the input voltage VAtimi may be a sinusoidal voltage whose frequency is, for example, between 10 Hz and 1 MHz. The voltage VAtim corresponds, for example, to the mains voltage.
    [0016] The control chip 7 comprises a full-wave rectifier circuit 100 comprising, for example, a diode bridge formed for example of four diodes. B13126 - Stacked LEDs and driver 27 The rectifier circuit 100 receives the supply voltage VALim and supplies a voltage VIN.
    [0017] The optoelectronic chip 6 comprises N groups of light-emitting diodes Gi, i ranging from 1 to N, where N is an integer between 2 and 200, preferably between 2 and 20. In the present embodiment, the N groups of diodes electroluminescent Gi, are connected in series. Each group Gi may comprise several sets of light-emitting diodes, for example connected in series. The series connection can be made directly at the optoelectronic chip 6. For example, each conductive pad 48i of a group of light-emitting diodes Gi is extended to come into contact with the conductive pad 46i + 1 of the light-emitting diode. neighbor Giil light emitting diodes. As a variant, the series of light-emitting diode groups can be connected in series by connection elements located in the control chip 7.
    [0018] The control chip 7 comprises a current source 102 connected in series with the light-emitting diode groups G1 to GN. The cathode of the last set of light emitting diodes of the group Gi is connected to the anode of the first set of light emitting diodes of the group Gi + 1, for i ranging from 1 to N-1. The control chip 7 further comprises N-1 controllable switches SW1 to SWN_1. Each switch SWi, i varying from 1 to N-1, is connected in parallel between the cathode of the last set of light emitting diodes of the group Gi and the anode of the first set of diodes 30 group Gi + 1. Each switch SW i, i controlled by a signal Si. The control chip 7 comprises a voltage adapted to provide a voltage signal VCS across the control source 7 further comprises a light emitting module of the variant of 1 to N -1, is further a 104 Sv sensor representative of the current 102. The control chip 106 receiving B13126 - Stacked LEDs and driver 28 the signal Sv and providing the signals S1 to SN_i_ control closing or opening switches SW1 to SWN_1. The control module 106 preferably corresponds to a dedicated circuit.
    [0019] The operation of the optoelectronic device 5 according to the embodiment shown in FIG. 8 is as follows, considering that the switches are perfect. The control module 106 is adapted to control the closing or opening of the switches SWi, i varying from 1 to N-1, as a function of the value of the voltage Vcs across the current source 102. For this purpose, the control module 106 is adapted to compare the voltage Vcs to at least one threshold. By way of example, the voltage VIN supplied by the rectifier bridge 100 is a rectified sinusoidal voltage comprising a series of cycles in each of which the voltage VIN increases from the null value passes through a maximum and decreases to zero. At the beginning of each cycle, all the switches SWi, i varying from 1 to N-1, are closed. As a result, the groups of light-emitting diodes G2 to GN are short-circuited and the voltage VIN is distributed between the group of light-emitting diodes G1 and the current source 102. The voltage VIN rises from the zero value. When the voltage across the group of light-emitting diodes G1 exceeds its threshold voltage, the group of light-emitting diodes G1 becomes on and begins to emit light. The voltage across the group G1 of light-emitting diodes is then substantially fixed and the voltage Vcs continues to increase with the voltage VIN. When the voltage Vcs exceeds a threshold, the module 106 controls the opening of the switch SW1. The voltage VIN is then distributed between the groups G1 and G2 of light-emitting diodes and the current source 102. When the voltage across the group G2 of light-emitting diodes exceeds its threshold voltage, the group G2 of light-emitting diodes becomes on and starts to emit light. The voltage across the group G2 of light emitting diodes is then substantially fixed and the voltage B13126 - Stacked LEDs and driver 29 VCS continues to increase with the voltage VIN. When the voltage VCS exceeds a threshold, the module 106 controls the opening of the switch SW2. These steps are repeated until the switch SWN_i_ is open. All light emitting diodes are then conducting. When the voltage VIN decreases from its maximum, the switches SWN_i_ to SW1 are successively closed in this order as the voltage VIN decreases, for example whenever the voltage VCS falls below a threshold.
    [0020] As a variant, when the switches SW1 to SWN_i_ are made by metal oxide-oxide field effect transistors or MOS transistors, instead of measuring the voltage VCS, it may be desirable to measure the voltages across the transistors.
    [0021] FIG. 10 shows another embodiment of the control chip 7. In this embodiment, the control chip 7 comprises a controllable current source 108i, i ranging from 1 to N, associated with each group of light-emitting diodes Gi . The control module 106 is adapted to independently enable or disable each current source 108i. Current sources 108i, i ranging from 1 to N, have a common terminal. At each current source 108i, i varying from 1 to N, is associated a sensor 110i providing the control module 106 with a signal SIi representative of the voltage across the current source 108i. The current source 108N has a terminal connected to the cathode of the last set of light emitting diodes of the GN group. Each current source 108i, i varying from 2 to N, has a terminal connected to the cathode of the last set of light emitting diodes of the group Gi.
    [0022] The operation of the optoelectronic device 5 according to the embodiment shown in Figure 9 is as follows. The control module 106 is adapted to successively activate each current source 108i, i varying from 1 to N-1, while deactivating the previously activated current source, as a function of the B13126 - Stacked LEDs and driver voltage across the terminals. each current source 102i, i varying from 1 to N. Various embodiments with various variants have been described above. It will be appreciated that those skilled in the art may combine various elements of these various embodiments and variants without demonstrating inventive step. By way of example, the electrical diagram of the optoelectronic device 5 shown in FIG. 9 or 10 may be implemented with the structure of the device 5 shown in FIG. 2 or the device 90 represented in FIG.
    权利要求:
    Claims (12)
    [0001]
    REVENDICATIONS1. An optoelectronic device (5; 90) comprising: a first integrated circuit (6) comprising a carrier comprising first and second opposing faces, groups (G1, G2, G3) of sets (D1, D2, D3) of electronic diodes; luminescent devices on the first side, each group comprising at least one set of light-emitting diodes connected in parallel and / or in series between first and second terminals, and each set (D1, D2, D3) of light-emitting diodes comprising a semiconductor element ( 201, 202, 203), or conical or frustoconical semiconductor elements connected in parallel, the first integrated circuit further comprising, in the support, first elements (52) for lateral electrical insulation of portions. of the support around each set, and on the second face, for each group, at least one first conductive pad (461, 462, 463) connected to the first terminal of a group and a second conductive pad (481, 482, 483) connected to the second terminal of the group; and a second integrated circuit (7) comprising third and fourth opposite faces, third conductive pads (70) on the third face electrically connected to the first and second conductive pads, the first integrated circuit being fixed on the third face of the second integrated circuit .
    [0002]
    Optoelectronic device according to claim 1, wherein the support comprises a first substrate (10) comprising opposing fifth and sixth faces (12, 14), the light-emitting diodes being located on the side of the fifth face, and comprising, for each together (D1, D2, D3), at least one second element (401, 402, 403) insulated conductor of the first substrate and passing through the first substrate from the fifth face to the sixth face and connected to one of the first pads conductors.
    [0003]
    Optoelectronic device according to claim 2, wherein the first elements (52) are adapted to electrically isolate portions (531, 532, 533) of the first substrate (10) underlying the light-emitting diodes. of each set (D1, D2, D3).
    [0004]
    Optoelectronic device according to claim 3, wherein the first elements (52) comprise insulating walls extending in the first substrate from the fifth face to the sixth face.
    [0005]
    Optoelectronic device according to any one of claims 1 to 4, wherein the second integrated circuit (7) comprises thermal drains (92) passing through the second integrated circuit from the third face to the fourth face.
    [0006]
    Optoelectronic device according to any one of claims 1 to 5, further comprising, for each set (D1, D2, D3), an electrode layer (301, 302, 303) covering each light-emitting diode of said set. and a conductive layer (321, 322, 323) covering the electrode layer around the light emitting diodes of said assembly.
    [0007]
    Optoelectronic device according to claims 2 and 6, wherein the second element (401, 402, 403) is in contact with the conductive layer (321, 322, 323).
    [0008]
    An optoelectronic device according to any one of claims 1 to 7, wherein the second integrated circuit (7) comprises a rectifier circuit (90) for receiving an alternating voltage (VALIM).
    [0009]
    Optoelectronic device according to any one of claims 1 to 8, wherein the first integrated circuit (6) comprises N groups (G1, Gi, GN) of sets of light-emitting diodes, where N is an integer ranging from 2 at 200, and wherein the second integrated circuit (7) comprises N-1 switches (SW1, SW1, SWN), each switch being connected to the first terminal or the second terminal of one of said groups (G1, Gi, GN ).
    [0010]
    Optoelectronic device according to claim 9, wherein the second integrated circuit (7) comprises N current sources (1081, 108i, 108N), each of N-1 of said current sources being connected to the first or second terminal of one of said groups (G1, Gi, GN).
    [0011]
    Optoelectronic device according to any one of claims 1 to 10, comprising fourth conductive pads (84) on the fourth face.
    [0012]
    Optoelectronic device according to any one of claims 1 to 11, wherein at least one of the groups (G1, G2, G3) comprises at least two sets (D1, D2, D3) of 10 light-emitting diodes.
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    公开号 | 公开日
    EP3410482A1|2018-12-05|
    US10304812B2|2019-05-28|
    FR3023066B1|2017-10-27|
    CN106663680B|2019-05-31|
    EP3161865A1|2017-05-03|
    EP3161865B1|2018-07-25|
    WO2016001200A1|2016-01-07|
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    EP3410482B1|2020-11-18|
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    法律状态:
    2015-06-26| PLFP| Fee payment|Year of fee payment: 2 |
    2016-01-01| PLSC| Publication of the preliminary search report|Effective date: 20160101 |
    2016-06-17| PLFP| Fee payment|Year of fee payment: 3 |
    2017-06-16| PLFP| Fee payment|Year of fee payment: 4 |
    2018-06-14| PLFP| Fee payment|Year of fee payment: 5 |
    2020-03-13| ST| Notification of lapse|Effective date: 20200206 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1456178A|FR3023066B1|2014-06-30|2014-06-30|OPTOELECTRONIC DEVICE COMPRISING LIGHT EMITTING DIODES AND A CONTROL CIRCUIT|FR1456178A| FR3023066B1|2014-06-30|2014-06-30|OPTOELECTRONIC DEVICE COMPRISING LIGHT EMITTING DIODES AND A CONTROL CIRCUIT|
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